Xenter is a technology in medicine company that is bringing medical devices to the digital age. Xenter is revolutionizing medicine by developing and launching smart/wireless guidewires and catheters that transmit data through a proprietary wireless network to our proprietary cloud that houses real time Physical Intelligence medical data.

Reports to: VP, Semiconductor Technology

Location: San Francisco Bay Area or Salt Lake City

Salary Range: $150K to $200K

Overview: 

You will be a key member in the ASIC team responsible for designing and verifying ultrasound transducer systems for medical imaging applications. You will architect the state-of-art acoustic sensing systems and the ASICs required to realize them. You will be expected to take high level user requirements and create a realizable system that meets these goals. This will include high level modeling of proposed solutions, along with creating detailed specifications of the requirements. This is a highly cross-functional role, and you will work with others to identify critical aspects of how the design will interact with the overall product. 

Responsibilities:

 · Work closely with the system architects to design world-class capacitive micromachined ultrasound transducer chips and IP blocks, which meet performance, power and area targets.

· As an ASIC Design Engineer, the individual’s primary responsibility will be RTL design

· This will include block/function definition, specification, design, simulation and unit level verification of digital functions on Mixed Signal ASICs

· Implement the function in Verilog RTL to specification

· Perform unit level testing on the RTL function

· Support the DV team by writing self-checking tests as required

· Collaborate with specialists from cross-disciplinary design and technology teams.

· Assist verification team in unit verification including test plan development.

· Assist with debug and bring-up.

Minimum Experience: 

• Strong knowledge of power reduction methodologies

• Experience in setting up Power Distribution architecture, power intent specification and validation methodology

• Flow automation scripts using Perl/Python, Tcl, and shell scripts

• Power user of industry standard RTL Design & Synthesis tools

• Knowledge of Extraction and STA methodology and tools

• Knowledge of best practices with respect to implementation of digital logic

• Understanding of digital design flow including RTL simulation, logic synthesis, timing constraints, timing closure, STA, back annotation of parasitics, gate level simulation, equivalence checking

• Working with Physical Design Team on STA, physical, power and logical issues

• Familiarity with lab equipment and debugging in the lab environment.

• Strong problem-solving skills and be able work in a fast paced collaborative environment. Be able to adapt to priority and task change quickly. Focus on details and getting tasks to completion. Independently explore new innovative ideas. 

• Excellent written and verbal communication skills and solid teamwork skills.

Minimum Education: 

  • PhD or Master degree in Electrical Engineering (Digital design/Digital Signal Processing/Low power applications) or related field.